The present invention relates to a semiconductor integrated circuit and system for reducing a power loss and noise caused by a parasitic element of a bonding pad, and specifically a semiconductor integrated circuit and system having a pad structure suitable for inputting and outputting a signal having a high frequency.
In the field of computers, the clock frequency has been increased in order to operate the computers at a higher speed. This requires memories and other peripheral devices to input and output a signal having a higher frequency in order to realize a higher speed interface.
Communication systems are also required to have a capability of inputting and outputting a signal having a higher frequency at a lower power loss and lower noise. For example, digital cell phones such as PHS phones use a signal having a frequency of 1 GHz to 2 GHz. Accordingly, it is required to transmit and receive such a signal at a lower power loss and with lower noise.
FIG. 20 shows a structure of a conventional communication system 200. The communication system 200 includes an RF section 210 for transmitting or receiving a signal and a baseband signal processing section 220 for processing a signal to be transmitted or a signal received. Conventionally, the RF section 210 and the baseband signal processing section 220 are formed on different chips. For example, the RF section 210 is formed on a GaAs substrate, and the baseband signal processing section 220 is formed on a silicon substrate.
A signal received by an antenna 201 is input to a low noise amplifier (LNA) 211 of the RF section 210 through a transmitting/receiving switch 202. The LNA 211 amplifies the received signal. The amplified signal is input to a mixer 213 though a filter 212. The mixer 213 mixes the signal output from the filter 212 and an oscillation signal output from an oscillator 214. The output from the mixer 213 is supplied to the baseband signal processing section 220.
The baseband signal processing section 220 includes a converter 221 and a digital signal processor (DSP) 222. The converter 221 converts the analog signal output from the mixer 213 into a digital signal. The DSP 222 processes the digital signal.
The digital signal processed by the DSP 222 is converted into an analog signal by the converter 221. A mixer 215 of the RF section 210 mixes the signal output from the converter 221 and an oscillation signal output from the oscillator 214. A power amplifier (PA) 216 amplifies the output from the mixer 215. The amplified signal is transmitted from the antenna 201 through the transmitting/receiving switch 202.
FIG. 21 schematically shows an equivalent circuit from the antenna 201 to the LNA 211. In FIG. 21, the transmitting/receiving switch 202 is omitted. The antenna 201 is connected to a bonding pad 103 through a signal line 217. The bonding pad 103 is connected to an input section of the LNA 211 through a signal line 218. Thus, a signal received by the antenna 201 is input to the LNA 211 through the bonding pad 103.
FIG. 22 shows a semiconductor circuit 100 including the bonding pad 103. The semiconductor circuit 100 includes a semiconductor substrate 101, an insulating layer 102 formed on the semiconductor substrate 101, and the bonding pad 103 formed on the insulating layer 102. On the semiconductor substrate 101, a MOS transistor 113 is also formed. Herein, it is assumed that the MOS transistor 113 is included in the input section of the LNA 211. A signal received by the antenna 201 is input to the bonding pad 103 as a voltage signal Vin. The bonding pad 103 is connected to a gate of the MOS transistor 113. Accordingly, the voltage signal Vin is applied to the gate of the MOS transistor 113.
FIG. 23 shows an equivalent circuit of the semiconductor circuit 100 shown in FIG. 22. In FIG. 23, Cp represents a parasitic capacitance existing between the bonding pad 103 and the semiconductor substrate 101, and Rp represents a parasitic resistance existing on a current path from the bonding pad 103 to a ground potential.
The impedance Z of the bonding pad 103 is represented by expression (1).
Z=(1/jxcfx89Cp)+Rpxe2x80x83xe2x80x83expression (1) 
Herein, Cp represents a parasitic capacitance, and Rp represents a parasitic resistance. Letter j is a symbol indicating an imaginary number. xcfx89=2xcfx80f, and f represents a frequency of the signal input to the bonding pad 103.
A power loss is generated by the impedance Z of the bonding pad 103.
The power loss Pa based on the impedance Z of the bonding pad 103 is represented by expression (2).
Pa=xcfx892Cp2Rp|Vin|2/(1+xcfx892Cp2Rp2)xe2x80x83xe2x80x83expression (2) 
Herein, Vin represents a voltage applied to the bonding pad 103.
FIG. 24 shows the relationship among the parasitic resistance Rp, the parasitic capacitance Cp and the power loss Pa. In FIG. 24, it is assumed that the frequency f of the signal input to the bonding pad 103 is 1 GHz.
In the conventional communication system 200, when the RF section 210 including the bonding pad 103 is formed on the GaAs substrate, the power loss Pa is hardly a problem because the parasitic resistance Rp is sufficiently large due to a very large resistance of the GaAs substrate.
However, the GaAs substrate is very expensive. Furthermore, when the RF section 210 is formed on the GaAs substrate, the RF section 210 and the baseband signal processing section 220 need to be formed on different chips from each other since it is preferable that the baseband signal processing section 220 is formed on a silicon substrate suitable for fabrication of a CMOS structure. This causes a problem that it is difficult to reduce the cost by forming main parts of the communication system 200 on a single chip.
When the RF section 210 and the baseband signal processing section 220 are formed on a single silicon chip, the parasitic capacitance Cp is about 1 pF and the parasitic resistance Rp is about 100 xcexa9. Therefore, the power lose based on the parasitic element of the bonding pad 103 is about several times as large as the power loss generated in the MOS transistor 113 (see FIG. 24). Accordingly, when the RF section 210 is formed on a silicon chip, the parasitic resistance Rp needs to be reduced.
It is understood from FIG. 24 that the power loss Pa can be reduced also by reducing the parasitic capacitance Cp. In order to reduce the parasitic capacitance Cp, the size of the bonding pad 103 needs to be reduced or the thickness of the insulating layer 102 needs to be increased. In consideration of the precision of the wire bonding, the size of the bonding pad 103 can only be reduced to a limited extent. It is difficult to increase the thickness of the insulating layer 102 in consideration of the other circuit elements formed on the semiconductor substrate 101. As can be appreciated, it is not very practical to reduce the power loss Pa by reducing the parasitic capacitance Cp. Accordingly, it is desirable to reduce the parasitic resistance Rp without substantially increasing the parasitic capacitance Cp.
FIG. 25 shows the relationship between the frequency f of the signal input to the bonding pad 103 and the power loss Pa. It is understood from FIG. 25 that, as the frequency of the signal input to the bonding pad 103 is increased, the parasitic resistance Rp needs to be reduced by a greater degree.
The parasitic resistance Rp also significantly influences the noise characteristic of the MOS transistor 113 connected to the bonding pad 103. The minimum noise Fmin of the MOS transistor 113 is generally represented by expression (3), which is referred to as the xe2x80x9cfukuixe2x80x9d equation.
Fmin=1+2xcfx80fKCgs((Rg+Rs/gm)xe2x80x83xe2x80x83expression (3) 
Herein, Cgs, represents a gate-source capacitance of the MOS transistor 113. K represents a transistor-inherent constant. Rg represents a gate resistance, and Rs represents a source resistance.
An increase in the parasitic resistance Rp is equivalent to an increase in (Rg+Rs). As a result of the increase in the parasitic resistance Rp, the minimum noise Fmin of the MOS transistor 113 is increased. In order to suppress the increase in the noise, the parasitic resistance Rp needs to be reduced.
A wireless receiver including an RF section and a baseband signal processing section formed on a single silicon substrate is disclosed in, for example, the following document.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996, pp. 880-889
FIG. 10 of the above-mentioned document shows a pad structure used in the RF section. The pad structure includes a first metal plate (Metal 1) and a second metal plate (Metal 2) facing each other. The first metal plate is formed on a silicon substrate in the state of being insulated from the silicon substrate. The second metal plate is formed on the first metal plate in the state of being insulated from the first metal plate. The first metal plate is connected to a ground potential.
With such a pad structure, when an input voltage is applied to the second metal plate, a current flowing from the second metal plate to the first metal plate flows from the first metal plate to the ground potential. Therefore, substantially no current flows in the silicon substrate. The parasitic resistance Rp in this case is represented by a sum of the resistance of the first metal plate and the interconnect resistance from the first metal plate to the ground. Accordingly, the parasitic resistance Rp is very small.
However, with the above-described pad structure, the first metal plate and the second metal plate face each other, and accordingly, the parasitic capacitance Cp is increased. The increase in the parasitic capacitance Cp causes the cutoff frequency ft of the MOS transistor connected to the second metal plate to be reduced. Furthermore, the increase in the parasitic capacitance Cp breaks the insulating layer by a large force applied to the second metal plate at the time of bonding. As a result, the second metal plate and the first metal plate may be undesirably shortcircuited, or the first metal plate and the silicon substrate may be undesirably shortcircuited.
The present invention for solving the above-described problems has an objective of providing a semiconductor integrated circuit and system for reducing a power lose and noise caused by a parasitic element of a bonding pad by reducing a parasitic resistance Rp without substantially increasing a parasitic capacitance Cp. Another objective of the present invention is to provide a semiconductor integrated circuit and system having a bonding pad suitable for inputting and outputting a signal having a high frequency.
A semiconductor integrated circuit according to the present invention includes a bonding pad; a semiconductor substrate electrically insulated from the bonding pad, the semiconductor substrate having a first region facing the bonding pad and a second region substantially surrounding at least a part of the first region; and setting means for setting the second region substantially at an equipotential.
The setting means includes voltage supply means for supplying a prescribed voltage; and connecting means for electrically connecting the voltage supply means to the second region of the semiconductor substrate.
In one embodiment, the connecting means includes a conductive section electrically connected to the voltage supply means and a plurality of contact portions discretely formed, and the plurality of contact portions each electrically connect the conductive section to the second region of the semiconductor substrate.
In one embodiment, a shape of the second region of the semiconductor substrate is determined by a shape of the conductive section.
In one embodiment, the conductive section has a shape substantially surrounding the first region of the semiconductor substrate.
In one embodiment, the conductive section has a plurality of basic cells arranged in an array.
In one embodiment, the connecting means includes a conductive section electrically connected to the voltage supply means and a contact portion continuously formed, and the contact portion electrically connects the conductive section to the second region of the semiconductor substrate.
In one embodiment, the second region of the semiconductor substrate is located outside the first region of the semiconductor substrate.
In one embodiment, the second region of the semiconductor substrate is located inside the first region of the semiconductor substrate.
In one embodiment, the semiconductor integrated circuit further includes a low resistance layer formed in at least a part of the first region of the semiconductor substrate.
In one embodiment, the equipotential is a ground potential.
A system according to the present invention includes a transmitting and receiving section for transmitting or receiving a signal; and a processing section for processing the signal to be transmitted or the signal received. The transmitting and receiving section includes a pad structure including a bonding pad, a semiconductor substrate electrically insulated from the bonding pad, the semiconductor substrate having a first region facing the bonding pad and a second region substantially surrounding at least a part of the first region, and means for setting the second region of the semiconductor substrate substantially at an equipotential.
In one embodiment, the transmitting and receiving section transmits or receives the signal through an antenna.
In one embodiment, the transmitting and receiving section transmits or receives the signal through an interface for connecting different semiconductor chips.
In one embodiment, the signal has a frequency of 100 MHz or more.
In one embodiment, the transmitting and receiving section and the processing section are formed on a single semiconductor chip.
In one embodiment, the transmitting and receiving section transmits and receives the signal.